As part of the ATLAS upgrade program the pixel detector will be equipped with an additional detector layer (IBL). The necessary off-detector readout electronics is connected via optical links and has to be largely compatible with existing hardware. With current FPGAs technology (Xilinx Virtex-5 and Spartan-6) almost all previously discrete functions can be integrated into FPGAs, simplifying the design significantly. In addition to the specific requirements of the optical channel connections - individual control of the mark-space ratio - a hybrid implementation of the calibration is investigated for IBL, which will replace the existing DSP-based solution. A fast FPGA processing unit builds histograms at full input speed, which are then analyzed on a host computer.
CPU and GPU-based algorithms are evaluated alternatively. The aim is to reduce the current significant processing time practically to the duration of data transmission by parallel execution of histogrammierung and analysis.
ATLAS Pixel Detector Video (ATLAS Experiment © 2013 CERN):